Frequency-domain equalization is performed in some communications systems, such as communications systems based on orthogonal frequency domain multiplexing (OFDM) and single-carrier systems with frequency-domain equalization (SC-FDE). An OFDM system transmits multiple data symbols at the same time over a media on a plurality of sub-carriers in a frequency band. The sub-carriers (both pilot and data sub-carriers) with the same time index together make up an OFDM symbol.
A variety of communication systems, including OFDM-based systems, use “soft bit” information (or metric) at the receiver for decoding information. Log-likelihood ratio (LLR) values are commonly used as the soft bit information. For example, in communication systems using convolution coding for FEC, LLR values are calculated for each information bit to be processed, and the LLR values are fed into a decoder, such as a Viterbi decoder, to decode the information bits. Other FEC schemes that require soft bit information include turbo codes and low-density parity-check (LDPC) codes.
FIG. 1 is a block diagram depiction of a conventional wireless OFDM receiver 100 which employs frequency-domain equalization and decoding using LLR values. Receiver 100 receives a RF signal in the form of symbols including a plurality of sub-carriers (tones) via antenna 101 as a sample data stream from the left to the right of the FIG. The analog front end (AFE) block 105 receives the signal from the antenna 101, which may include a variable gain amplifier (VGA), down-converter (or mixer), RF/analog filters and analog-to-digital (A/D) converter.
Cyclic prefix (CP) removal block 108 after the AFE block 105 can be used to remove the doubled (redundant) CP on an OFDM frame preamble structure for the IEEE 802.15.4 g standard having an LTF structure including two LTF symbols. More generally, in OFDM systems (including wireless local area networks (LANs)), CP removal block 108 removes the single CP included in the preamble.
After CP removal by CP removal block 108, the samples are then converted from serial to parallel (1 to N) by serial to parallel (S/P) conversion block 110. The receiver 100 includes a FFT block 115 which performs a Fast Fourier Transform (FFT) on the data from S/P conversion block to generate a plurality of frequency-domain samples, and then feeds the results to the frequency-domain equalization/combination block 120. Frequency-domain equalization/combination block 120 receives channel estimates for the respective sub-carriers from the channel estimation block 125 shown.
Frequency-domain equalization/combination block 120 is operable to compensate the received signal for linear distortion from the channel (e.g., multipath effects). Parallel to serial conversion is performed by parallel to serial (P/S) conversion block 130. LLR calculation block 135 receives (i) channel estimates from channel estimation block 125 and (ii) noise variance estimates from noise variance estimation block 145 which has an input tap coupled to the output of the FFT block 115. LLR calculation block 135 is operable to generate LLR values using (i) and (ii).
LLR calculation block 135 is coupled to the output of P/S conversion block 130, and to the input of forward error correction (FEC) decoding block referred to herein as decoder 140, which using the LLR values from the LLR calculation block 135 recovers bits from the original (transmitted) data stream. In real-world systems, the signal processing modules (all blocks except antenna 101 and AFE block 105) are controlled by software run by a computing device, such as a digital signal processor (DSP) or application specific integrated circuit (ASIC).
Decoders 140 such as the Viterbi decoder are generally able to process soft bit information with a finite-bit resolution (e.g., 4 bits). The LLR values which are theoretically derived by conventional LLR calculation block 135 have a very wide range in value, depending on the operating condition of system. In particular, the LLR value scales in proportion to the SNR (signal-to-noise ratio) of the channel, as well as the channel gain. This makes properly quantizing the soft bit information important to avoid a performance loss in FEC decoding. There is a need for a simple but efficient method that enables finite-bit representation of log-likelihood ratio (LLR) values.